VLSI Design Flow: RTL to GDS

Participants join the VLSI Design Flow: RTL to GDS course to gain a clear and practical understanding of the complete chip design lifecycle, starting from RTL design and ending with GDSII tape-out. The course helps bridge the gap between academic concepts and real-world industry workflows by explaining how each stage of VLSI design—such as synthesis, floorplanning, placement, routing, timing analysis, and verification—fits together in an actual project. It equips learners with industry-relevant knowledge and terminology, making them better prepared for VLSI internships, jobs, and advanced studies, while building confidence in understanding how modern integrated circuits are designed and manufactured.

1. Logic Optimization

2. Formal Verification

3. Static Timing Analysis

4. Constraints

5. Technology Mapping

6. Timing-driven Optimization

7. Technology Library and Constraints